Programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs) and application specific integrated circuits (ASICs) are commonly-used integrated circuit (IC) devices. PLDs allow a user (e.g., a circuit designer) to design and operate customized sets of logic functions using a single chip. The widespread use of PLDs stems from this flexibility.
A conventional PLD such as an FPGA includes logic resources such as configurable logic blocks (CLBs), input/output blocks (IOBs), and a configurable interconnect structure (CIS). The logic resources are programmable to implement a user's circuit design.
FIG. 1 shows a simplified schematic diagram of a conventional FPGA 100. FPGA 100 comprises an array of CLBs 102, a plurality of IOBs 104, a CIS 110, a configuration port 120, and a configuration control circuit 130. CIS 110 includes a plurality of programmable switch matrices (PSMs) 106 that allow signals to be routed as desired between CLBs 102 and IOBs 104. CLBs 102 can be configured to perform various logic functions, while IOBs 104 can be configured to drive output signals or receive input signals from various pins (not shown) of FPGA 100.
FPGA 100 can also include dedicated internal logic. Dedicated internal logic performs specific functions and can be only minimally configured or are not configurable by a user. Configuration port 120 is an example of dedicated internal logic. Other examples may include power distribution grids (not shown) and dedicated clock nets (not shown).
FPGA 100 is illustrated with 9 CLBs 102, 12 IOBs 104, and 4 PSMs 106 for clarity only. Actual FPGAs may contain thousands of CLBs, hundreds of IOBs, and thousands of PSMs. The ratio of the number of CLBs, IOBs, and PSMs can also vary.
Logic resources such as CLBs 102 and IOBs 104 generally include one or more function generators and one or more storage elements (e.g., flip-flops) connected by programmable interconnect lines, while logic resources used for signal transmission and routing such as PSMs 106 generally include only the programmable interconnect lines. However, each CLB 102, IOB 104, and PSM 106 also includes at least one programmable element (not shown) that is configured by a configuration bit from a configuration memory cell (FIG. 1a). Therefore, a single logic resource having multiple programmable elements is connected to multiple configuration memory cells. All the configuration memory cells associated with a particular logic resource must be programmed (or set to a default value) before that logic resource can perform its desired function.
FIG. 1a shows a conventional configuration memory cell 150. Typically, one or more such configuration memory cells are used to control each programmable element in an FPGA. Configuration memory cell 150 is a 5-transistor memory cell comprising a conventional latch 156 (i.e., a 4-transistor device) and a select transistor 152. Select transistor 152 is coupled between a configuration bus 160 and an input terminal of latch 156, with the control terminal of select transistor 152 being coupled to a configuration select line 154. During the configuration process, data received at configuration port 120 is passed to configuration bus 160. Configuration control circuit 130 (FIG. 1) controls whether a desired configuration bit from configuration bus 160 can be loaded into latch 156. To load latch 156, configuration control circuit 130 pulls configuration select line 154 to a logic high state. During operation of the FPGA, latch 156 provides the stored configuration bit to the programmable element of the logic resource (i.e., CLB, IOB, or PSM) associated with configuration memory cell 150.
The configuration, or "context", of an FPGA is defined by the set of configuration bits that configures the programmable elements of the logic resources of the FPGA. The set of configuration bits associated with a particular user-defined context (UC) is referred to as a "memory slice". A configuration data stream is used to load a particular memory slice defining a user-defined context into the configuration memory cells of an FPGA. Configuration port 120 provides an interface for external configuration devices (not shown) to provide the configuration data stream to FPGA 100. The configuration memory cells are typically daisy-chained together by a configuration bus (not shown) and are thus programmed sequentially under the control of configuration control circuit 130. Because of the serial nature of the programming process, FPGA configuration can be time-consuming. Specific examples for configuring various FPGAs can be found on pages 4-54 to 4-79 of "The Programmable Logic Data Book," published in September, 1996 by Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference. (Xilinx, Inc., owner of the copyright, has no objection to copying these and other pages referenced herein but otherwise reserves all copyright rights whatsoever.)
A UC becomes "active" once its associated memory slice controls the programmable elements of a PLD. Once active, the operation of the UC can be verified by a logic analysis circuit that analyzes state data generated at specific locations ("test nodes") within the PLD. The logic analysis circuit typically reads and processes the state data in response to a trigger signal. The trigger signal can be generated by pre-specified events within the PLD or can simply be a periodic, clocked function.
The logic resources of a conventional PLD can be configured to provide a logic analysis circuit, i.e., a circuit that provides stimulus for, observes, and/or analyzes logic values in a circuit under test. However, a conventional PLD is generally heavily utilized, leaving few, if any, available logic resources free for the logic analysis circuit. This resource limitation dictates that the logic analysis circuit be external to the PLD (off-chip). However, the state data from the test nodes in the PLD must still be distributed to the external logic analysis circuit at appropriate times. In a conventional PLD, a portion of the logic resources are configured as "probe circuits", which provide both triggering functions and the transference of state data from the test nodes to various pins. Although the probe circuits consume a portion of the available logic and routing resources, this portion is much smaller than would be required by a logic analysis circuit.
FIG. 2 shows a conventional FPGA 200 having a portion of its logic and routing resources configured as probe functions. FPGA 200 is similar to FPGA 100, comprising CLBs 102a-102i surrounded by IOBs 104a-104l, a CIS 110, a configuration port 120, and a configuration control circuit 130. CLBs 102b and 102f and IOBs 104b and 104e (shown shaded) are configured to provide probe circuits for testing of the UC in the remaining CLBs and IOBs.
The use of probe circuits to gather the data for verification of a UC provides great flexibility in the selection of trigger logic and test nodes. The logic and routing resources used to provide the probe circuits are from the same pool of resources used by the active UC. Therefore, the probe circuits have direct access to the test nodes of the active UC.
However, the use of otherwise general-purpose CLBs and IOBs to create the probe circuits reduces the logic and routing resource available for the desired UC. Therefore, in heavily utilized PLDs, resource limitations may curtail the effectiveness of probe circuit testing. Either a reduced number of probe circuits may be used to perform partial testing of the UC, or the UC itself may be only partially configured (i.e., portions of the desired logic may be eliminated from the UC), to make additional logic and routing resources available for the probe functions. Neither option is completely satisfactory. Partial testing can be time-consuming if multiple test runs must be made to cover the full range of UC operation. In addition, partial testing may fail to detect problems associated with the full UC. On the other hand, partially configuring the UC can potentially alter the performance of the UC. Further, the inclusion of probe functions in the PLD along with the UC can affect the performance of the UC. The additional gates, gate activity, and routing modifications can generate noise and signal delays in the UC, leading to erroneous test results.
Another problem associated with probe function testing is that a large number of pins may be required to transmit the state data to the external logic analyzer. Typically, one pin is used to transfer the state data from each test node being examined. The active UC requires a certain number of pins for its own data input/output activity. Because the total number of pins in a PLD package is limited, typically either the UC must be modified or the test abridged.
To reduce the number of pins required for test purposes, a technique called Level Sensitive Scan Design (LSSD) testing is sometimes used. In LSSD testing, the state data from the test nodes are combined into a single scan chain that is transmitted to the logic analyzer. The scan chain is transmitted to the logic analyzer through a single pin, thereby minimizing the number of pins required for the testing process. However, because of this serial transfer of the state data, the time required for testing is increased. Also, the lengthy data output delays required by the LSSD testing process make it impractical for verification of high-speed UCs.
An alternative method for testing the operation of a UC is the Readback process, developed by Xilinx, Inc. and used in their XC4000.TM. series FPGAs. The Readback process addresses some of the resource limitation and signal delay issues of probe circuit testing. FIG. 3 shows a simplified circuit diagram of an FPGA 300, which is consistent with the XC4000-series FPGAs from Xilinx, Inc. FPGA 300 is similar to FPGA 100 (FIG. 1), and comprises an array of CLBs 102 surrounded by a ring of IOBs 104 and interconnected by a CIS 110 including multiple PSMs 106. As in FPGA 100, CLBs 102, IOBs 104, and PSMs 106 in FPGA 300 are configured by a configuration control circuit 130 using data received through a configuration port 120. However, FPGA 300 further includes readback logic resources 302 and readback routing resources 304. Readback logic resources 302 comprise a trigger net (not shown) that can be connected to any IOB 104 by readback routing resources 304. When a low-to-high transition takes place on the trigger net, readback logic resources 302 begin shifting out a data stream that reports the configuration bits of FPGA 300. Readback logic resources 302 can be configured to also include the contents of all flip-flops and latches in FPGA 300 in the readback data stream. This data stream is fed to an IOB that routes the data stream to an external logic analyzer (not shown).
Because the Readback technique utilizes dedicated readback trigger and data collection resources, resource limitation issues are alleviated. None of the logic and routing resources required by the UC are consumed by the testing functions, thereby allowing the full UC to be operated. In addition, as in LSSD testing, only one pin is needed to transmit the data stream to the external logic analysis circuit.
However, as with LSSD testing, the Readback technique can be time-consuming due to the serial nature of the output data stream. This problem is exacerbated by the fact that the data stream format provided by the Readback technique includes both the configuration and state data for the UC, even though the logic analysis circuit generally does not require all the configuration and state data. The extraneous data decreases the effective output rate for the data of interest, while forcing the logic analysis circuit to spend additional processing time to extract the relevant information. Another limitation of the Readback technique is that because the trigger net can monitor only a single IOB 104 (i.e., a single node), the triggering conditions that can be applied are limited. Test nodes within the array of CLBs 102 are isolated from the trigger net and therefore cannot be monitored for use with the trigger logic.
Accordingly, it is desirable to provide a method and apparatus for providing rapid logic analysis for an IC without interfering with normal IC operation.